Test access port controller and a method of effecting communication using the same

Abstract:

There is disclosed a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test mode of operation the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic mode of operation diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access port controller.

Body:

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